For those interested in numbers, see Young-Ho’s Google Scholar
Quantifying the Impact of Monolithic 3D (M3D) Integration on L1 Caches
Y.-H. Gong, J. Kong, and S. W. Chung
IEEE Transactions on Emerging Topics in Computing (JCR Q1 IF: 4.989), published online
Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency
C. T. Do, Y.-H. Gong, C. H. Kim, S. W. Kim, and S. W. Chung
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Lausanne, Switzerland, July 2019.
A High Speed Multiply-Accumulate (MAC) Unit: Case Studies on 3D Stacked FPGA and ASIC
Y. S. Lee, K. M. Kim, S. J. Nam, Y. -H. Gong, S. W. Kim, and S. W. Chung
Design Automation Conference (DAC), Las Vegas, USA, June 2019.
(poster presented in WIP (Work-in-Progress) session)
Thermal Modeling and Validation of a Real-World Mobile AP
Y. -H. Gong, J. J. Yoo, and S. W. Chung
IEEE Design & Test (IF: 3.022), vol. 35, no. 1, pp. 55-62, February 2018.
Thermal Modeling and Validation of a Real-World Mobile AP
Y. -H. Gong, J. J. Yoo, and S. W. Chung
IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.
(This summary paper (originally published in IEEE Design and Test) was presented in TCAS session.)
Architecting Large-Scale SRAM Arrays with Monolithic 3D Integration
J. Kong, Y. -H. Gong, and S. W. Chung
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Taipei, Taiwan, July 2017.
Towards Refresh-optimized EDRAM-based Caches with a Selective Fine-grain Round-robin Refresh Scheme
J. Kong, Y. -H. Gong, and S. W. Chung
Microprocessors and Microsystems (IF: 1.045), vol. 49, pp. 95-104, March 2017.
Exploiting Refresh Effect of DRAM Read Operations: A Practical Approach to Low-power Refresh
Y. -H. Gong and S. W. Chung
IEEE Transactions on Computers (IF: 3.131), vol. 65, no. 5, pp. 1507-1517, May 2016.
Exploration of Temperature-aware Refresh Schemes for 3D Stacked eDRAM Caches
Y. -H. Gong, J. M. Kim, S. K. Lim, and S. W. Chung
Microprocessors and Microsystems (IF: 1.045), vol. 42, pp. 100-112, May 2016.
Performance and Cache Access Time of SRAM-eDRAM Hybrid Caches Considering Wire Delay
Y. -H. Gong, H. B. Jang, and S. W. Chung
International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, March 2013.